Data through FY2026 Q3 (Jun 30, 2026)
Principal Engineer, VLSI Design Engineering
Occupation profile for Principal Engineer, VLSI Design Engineering covers 11 filings across the reporting window. FY2025 certified median offer: $165,275.
- FY2025 certified median
- $165,275
- Total filings
- 11
- FY2025 25th–75th percentile
- $151,091–$167,512
- Top employer
- Sandisk Technologies, Inc.
| Fiscal year | Filings | Median | 25th percentile | 75th percentile |
|---|---|---|---|---|
| FY2025 | 11 | $165,275 | $151,091 | $167,512 |
FY2026 is partial (*). Its filing totals are not comparable to a full fiscal year.
Median offer by fiscal year
Top employers
- Sandisk Technologies, Inc.11 filings
Top cities
- Folsom4 filings
- Milpitas4 filings
- Hayward1 filings
- San Jose1 filings
- Santa Clara1 filings
Filings by employer and title
Prevailing wages by area and occupation
The OFLC wage year runs from July through June. Worksites use the area of the most frequently reported county with a matching wage area for their city.
| Wage year | Area | SOC | Level I | Level II | Level III | Level IV |
|---|---|---|---|---|---|---|
| 2026-27 | San Jose-Sunnyvale-Santa Clara, CAArea 41940 | 17-2072 | $124,405 | $155,896 | $187,408 | $218,899 |
| 2026-27 | Sacramento-Roseville-Folsom, CAArea 40900 | 17-2072 | $105,602 | $127,088 | $148,554 | $170,040 |
| 2026-27 | San Francisco-Oakland-Fremont, CAArea 41860 | 17-2072 | $108,846 | $138,528 | $168,189 | $197,870 |