Data through FY2026 Q3 (Jun 30, 2026)
Altera Corporation · FPGA Silicon Design Verification Engineer
Employer and title profile for Altera Corporation · FPGA Silicon Design Verification Engineer covers 9 filings across the reporting window. FY2026 certified median offer: $183,230.
- FY2026 certified median
- $183,230
- Total filings
- 9
- Lowest–highest certified offer
- $94,414–$216,091
- Latest decision date
- 2026-06-11
All-years certified median $151,895 · Range $94,414 to $216,091
Median offer by fiscal year
Latest filings
| Case | Decision | Status | City | Annual offer |
|---|---|---|---|---|
| I-200-26156-984375 | 2026-06-11 | Certified | San Jose | $216,091 |
| I-200-26028-596128 | 2026-02-04 | Certified | Manteca | $183,230 |
| I-200-26014-557617 | 2026-01-22 | Certified | San Jose | $216,091 |
| I-200-25317-403475 | 2025-11-20 | Certified | Austin | $161,179 |
| I-200-25317-403497 | 2025-11-20 | Certified | Hillsboro | $94,414 |
| I-200-25202-190170 | 2025-07-28 | Certified | Austin | $135,907 |
| I-200-25168-099605 | 2025-06-25 | Certified | San Jose | $120,108 |
| I-200-25128-952964 | 2025-05-15 | Certified | San Jose | $151,895 |
| I-200-25113-893386 | 2025-04-30 | Certified | San Jose | $151,895 |